Assignment No. 03
(Non-Graded Assignment)
Semester: Spring 2014
CS501: Advanced Computer Architecture
Announced date 30 June, 2014
Due Date 07 July, 2014
Total Marks: 15
Instructions
please read the following instructions carefully before assignment submission.
It should be clear that your assignment will not get any credit if:
The assignment is submitted after the due date.
The submitted assignment does not open or file is corrupt.
The assignment is found to be copied from the internet.
The assignment is found to be copied from other student.
The assignment submitted is not according to required file format (.doc).
Objective
The objective of this assignment is:
To assess your overall understanding of Computer Architecture and Organization
To assess your overall understanding of Computer Instructions
To assess your overall understanding of Fetch, Decode and Execute Cycle clock in pipeline structure.
Note:
The assignment should be in .doc format.
Assignment .03 (Non-Graded) covers lecture 17-25. You can also consult reference books for help.
Students are advised to submit their assignment as early as possible in order to avoid any sort of inconvenience like Load shedding etc.
Question: Marks 15
Students are required to explain how the given SRC (Simple RISC computers) code will be executed through the five stages of a pipelined based processor.
Addresses
Instructions
400
add r1, r2, r3
404
ld r5, [5(r7)
408
br r6
412
str r4, 56
…
4…
.
Marking scheme (Total marks 15)
3 marks for each step (3*5 = 15)
GOOD LUCK
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